PDIUSBD12

General description

The PDIUSBD12 is a cost- and feature-optimized USB peripheral controller. It is normally used in microcontroller-based systems and communicates with the system microcontroller over the high-speed general-purpose parallel interface. It also supports local DMA transfer.

This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the wide variety available. This flexibility cuts down development time, risks and costs, by allowing the use of the existing architecture, minimizing firmware investments. This results in the fastest way to develop the most cost-effective USB peripheral solution.

The PDIUSBD12 fully conforms to Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s). It is also designed to be compliant with most device class specifications: imaging class, mass storage devices, communication devices, printing devices and human interface devices. The PDIUSBD12 is ideally suited for many peripherals, such as printer, scanner, external mass storage (Zip drive) and digital still camera. It offers an immediate cost reduction for applications that currently use SCSI implementations.

The PDIUSBD12 low suspend power consumption along with the LazyClock output allows for easy implementation of equipment that is compliant to the ACPI, OnNow and USB power management requirements. The low operating power allows the implementation of bus powered peripherals.

It also incorporates features, such as SoftConnect, GoodLink, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into peripherals.

Features

• Complies with Universal Serial Bus specification Rev. 2.0
• Supports data transfer at full-speed (12 Mbit/s)
• High performance USB peripheral controller with integrated SIE, FIFO memory, transceiver and voltage regulator
• Compliant with most device class specifications
• High-speed (2 MB/s) parallel interface to any external microcontroller or microprocessor
• Fully autonomous DMA operation
• Integrated 320 B of multi-configuration FIFO memory
• Double buffering scheme for main endpoint increases throughput and eases real-time data transfer
• Data transfer rates: 1 MB/s achievable in bulk mode, 1 Mbit/s achievable in isochronous mode
• Bus-powered capability with very good EMI performance
• Controllable LazyClock output during suspend
• Software-controllable connection to the USB bus (SoftConnect)
• Good USB connection indicator that blinks with traffic (GoodLink)
• Programmable clock frequency output
• Complies with the ACPI, OnNow and USB power management requirements
• Internal Power-On Reset (POR) and low-voltage reset circuit
• Available in SO28 and TSSOP28 pin packages
• Full industrial grade operation from -40 Cel to +85 Cel
• Full-scan design with high fault coverage (> 99 pct) ensures high quality
• Operation with dual voltages: 3.3 V +- 0.3 V or extended 5 V supply range of 4.0 V to 5.5 V
• Multiple interrupt modes to facilitate both bulk and isochronous transfers

Products/packages

Pricing/ordering/availability

Applications

Related applications
Motherboard components

Block diagrams/pinning

Technical documents

Application Notes

AN10010_5; ISP1181A/ISP1181B/ISP1183 Frequently Asked Questions (27-Nov-07)

AN10035_1; Comparing energy efficiency of USB at full-speed and high-speed rates (01-Oct-03)

AN10051_4; PDIUSBD12 Frequently Asked Questions (09-Mar-07)

PDIUSBD12_DMA_MODE; Application Note: Using PDIUSBD12 in DMA mode (01-Aug-98)

PDIUSBD12_HITACHI_H8S_2357; Application Note: Interfacing PDIUSBD12 to Hitachi H8S/2357 (01-Aug-98)

Support Documents

D12_PC_sch_ver2.0; D12 ISA BRIDGING BOARD/D12 EVALUATION BOARD (1998-04-23)

d12_masssto_usb2ide_cf_guide; D12 Mass Storage Kit (USB-to-CompactFlash (tm) or IDE) (2000-12-01)

D12Smart_Sch_Ver1.0; D12 SMART Evaluation Board (1999-06-06)

D12EPP_Sch_Ver1.0; D12 USB-EPP Evaluation Main Board/EPP-SRAM Evaluation Daughter Board (1998-08-13)

D12MassStorage_Sch_Ver1.0; D12MassStorage (2000-08-28)

PDIUSBD12_PROGRAMMING_GUIDE; Firmware Programming Guide for PDIUSBD12 Version 1.0 (1998-09-01)

web; For errata sheet: contact NXP support ()

75015937; NXP USB products (01-Feb-07)

D12PCKitMan; PDIUSBD12 Evaluation Board (PC Kit) User's Manual (1998-09-01)

UM10053_1; PDIUSBD12 USB EPP Eval Kit (2004-05-12)

75010515; PDIUSBD12 USB Interface Device with Parallel Bus (2002-06-01)

75014395; Your connection to I 2 C,UART,CAN,and USB Connecting with Philips Wired Connectivity (2005-04-01)

Parametrics/similar products

Similar products

PDIUSBD12 links to the similar products page containing an overview of products that are similar in function or related to the type number(s) as listed on this page. The similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category.

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